Semiconductor devices include one or more integrated circuits that can be used to store data, process electronic signals, etc. Such semiconductor devices are used in virtually all modem electronic devices. There are several different types of semiconductor devices used in modem electronics including, for example, memory devices, electronic signal processors, devices for capturing or acquiring images, etc. Each of these semiconductor devices typically comprise a plurality of transistors, which can be used as gates or switches for electrical signals.
FIG. 1 is a schematic cross-sectional view of a conventional transistor 10 that may be used in a memory cell of a non-volatile memory device. The transistor 10 may be fabricated on or in a substrate 11, which may comprise a doped semiconductor material. The transistor 10 shown in FIG. 1 has a dual gate structure and includes a control gate 12, a floating gate 14, a source 16, and a drain 18. The source 16 and drain 18 may comprise, for example, doped regions in or on the substrate 11, which itself may be doped of opposite polarity relative to the source 16 and the drain 18. By way of example and not limitation, the source 16 and drain 18 may comprise n-doped regions in or on the substrate 11, and the substrate 11 may be p-doped at least in the region thereof between the source 16 and the drain 18 so as to provide an npn type structure in the substrate 11 below the floating gate 14. The floating gate 14 is electrically isolated from the control gate 12 by the so-called “inter-gate dielectric” material 20, and from the underlying substrate 11 (including the source 16 and the drain 18) by another dielectric material, which is often referred to as the “tunnel dielectric” material 22 or the “tunnel oxide.” The floating gate 14 also may be further electrically isolated from surrounding structures by a passivation layer 24.
The control gate 12 and the floating gate 14 are capacitively coupled to one another (i.e., positioned such that an electrical capacitance may be generated therebetween), and the control gate 12 is used to selectively charge the floating gate 14. In other words, when a sufficient voltage is applied to the control gate 12, electrons may be caused to “tunnel” through the tunnel dielectric material 22 from the substrate 11 to the floating gate 14, where they may remain even after the voltage applied to the control gate 12 is interrupted, since the floating gate 14 is electrically isolated by the inter-gate dielectric material 20, the tunnel dielectric material 22, and the passivation layer 24.
When a given reading voltage is applied between the source 16 and the drain 18, the presence of electrons on the floating gate 14 may cause a relatively lower current to flow between the source 16 and the drain 18 (and the memory cell may be characterized as representing a “0”), while the absence of electrons on the floating gate 14 may allow a relatively higher current to flow between the source 16 and the drain 18 (and the memory cell may be characterized as representing a “0”).
By utilizing a floating gate 14 that is electrically isolated by the inter-gate dielectric material 20, the tunnel dielectric material 22, and the passivation layer 24, any electrons present on the floating gate 14 may remain thereon even after power to the memory device is interrupted. As a result, memory devices having transistors that include such dual-gate structures are considered non-volatile.
Other types of semiconductor devices including, for example, electronic signal processors and devices for acquiring or capturing images (often referred to as “imagers”), also may include a plurality of transistors for storing data therein. In other words, such semiconductor devices may have subsystems of components that comprise memory. As a result, such semiconductor devices also may comprise transistors such as that described above.
As integrated circuit fabrication processes improve, the feature sizes of the various elements in the integrated circuits are reduced so as to enable the fabrication of smaller semiconductor devices and/or semiconductor devices having increased cell densities, and, hence, higher data storage capacities.
As previously mentioned, a capacitance is generated between the floating gate and the control gate in transistors having a dual gate structure. Such transistors are conventionally fabricated side-by-side in an array on a substrate. As a result, a capacitance also may be generated between the floating gates of adjacent transistors in the array. Such inter-transistor capacitances can negatively affect the operation of the semiconductor device.
The coupling ratio (CR) of a semiconductor device (e.g., a memory device) may be defined as the ratio of the capacitance CFG-CG between the floating gate and the control gate in each transistor to the capacitance CFG-FG between the floating gates of adjacent transistors (i.e., CR=CFG-CG/CFG-FG). It is typically desirable to maximize the coupling ratio (when the coupling ratio is defined in this manner) to enhance the reliability and performance of the semiconductor device. As the feature size of the various elements (e.g., the size of the various elements of the transistors, as well as the spacings therebetween) in the integrated circuits of such semiconductor devices are scaled downward, it may be more difficult to maintain a high coupling ratio due, at least in part, to the decreasing surface area between opposing surfaces of the control gate and the floating gate and the decreasing spacing or distance between the floating gates in adjacent transistors. The decreasing surface area between opposing surfaces of the control gate and the floating gate may cause a decrease in the capacitance CFG-CG between the floating gate and the control gate in each transistor, and the decreasing spacing or distance between the floating gates in adjacent transistors may cause an increase in the capacitance CFG-FG between the floating gates of adjacent transistors.
For the reasons stated above, and for other reasons which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for improved floating gate transistors, such as those that exhibit relatively high coupling ratios, and that can be scaled to smaller feature sizes without decreasing the coupling ratio to an unacceptable level.